Variable Declaration
Declaration ---- used in ----> Process
Procedure
Function

Syntax

variable variable_name : type;
variable variable_name : type := initial_value;

See LRM section 4.3.1.3

Rules and Examples

variable HEIGHT : integer := 8;
variable COND : boolean := true;
variable IN_STRING : string(1 to 80);
variable M,N : bit := '1';
variable I : integer range 0 to 3;
variable MAKE_FRAME_STATE :
    T_MAKE_FRAME_STATE := RCV_HIGH;

A Variable may be given an explicit initial value when it is declared. If a variable is not given an explicit value, it's default value will be the leftmost value ('left) of its declared type. 
variable I : integer range 0 to 3;
-- initial value of I is 0
variable X : std_ulogic;
-- initial value of X is 'U'

Variables within subprograms (functions and procedures) are initialised each time the subprogram is called: 
function PARITY (X : std_ulogic_vector)
                 return std_ulogic is
  variable TMP : std_ulogic := '0';
begin
  for J in X'range loop
    TMP := TMP xor X(J);
  end loop; --no need to initialise TMP
  return TMP;
end PARITY;

Variables in processes, except for "FOR LOOP" variables, receive their initial values at the start of the simulation time (time = 0 ns) 
process (A)
   variable TMP : std_ulogic := '0';
begin
   TMP := '0';
   -- in this example we need to reset
   -- TMP to '0' each time the process 
   -- is activated
   for I in A'low to A'high loop
      TMP := TMP xor A(I);
   end loop;
   ODD <= TMP;
end process;

Synthesis Issues

Variables are supported for synthesis, providing they are of a type acceptable to the logic synthesis tool.

In a "clocked process", each variable which has its value read before it has had an assignment to it will be synthesised as the output of a register.

In a "combinational process", reading a variable before it has had an assignment may cause a latch to be synthesised.

Variables declared in a subprogram are synthesised as combinational logic.

Whats New in '93

In VHDL-93, shared variables may be declared within an architecture, block, generate statement, or package: 

shared variable variable_name : type;
Shared variables may be accessed by more than one process. However, the language does not define what happens if two or more processes make conflicting accesses to a shared variable at the same time.