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A value, function, type, range, signal, or constant that may be associated with one or more named entities in a description.
attribute attribute_name: type; -- attribute declaration
attribute attribute_name of item : item_class is expression; -- attribute specification
VHDL allows attaching additional information to design elements through new attributes for specified types. In order to assign an attribute to a given design element, attribute specification is used. The values assigned this way can be referred in the expressions through declared attribute name.
The attribute declaration defines a new attribute within the scope of the given declarative area. It consists of an identifier specification, which represents user defined attribute and type mark that indicates value type for this attribute. A user-defined attribute can be of any VHDL type, except for an access type, file type, and any complex type with elements of any of the two types. See Example 1.
Attribute specification assigns an attribute declared earlier to a chosen named entity. The named entities that can be assigned attributes are: entity, architecture, configuration, procedure, function, package, type, subtype, constant, signal, variable, component, label, literal, units, group, or file. The named entities are enumerated in entity names list. In such a way the attribute is assigned to a given language unit. Finally, the attribute specification contains an expression, which sets an attribute value for the entities listed in the specification. See Example 2.
The attribute specification for most named entities must be declared together with declarations of those entities. For some entities, however, the attribute specification is written in other places.
The attribute specification for library units such as entity, architecture configuration and package cannot be directly placed in the library, which contains library unit declarations. Because of that, the attribute specification is placed in the declaration part of named entity (Example 3).
The attribute specification for a subprogram must be declared in the same visibility region as the subprogram's declaration. In case of overloaded procedures and functions, signatures must be used to point to the subprogram to which the attribute is assigned (Example 4). If no signature is used the attribute relates to all subprograms with the same name.
Functions declared as the operators are always overloaded, and that is why they always require the signature in the attribute specification to differentiate functions (Example 5).
Attribute specifications for ports and generic parameters are placed in the declaration part of the design entity or the block statement to which they belong. The attribute specifications for formal parameters of subprograms are placed in the declaration part of these subprograms (Example 6).
Attribute specifications for labeled statements cannot be located directly in the place of the statements' declarations. Therefore, the attribute specifications for the label connected with any concurrent or sequential statements are placed in the declaration part before the occurrence of a given statement (Example 7).
In case of the sequential statement labels, the attribute specification is placed in the declaration part of the process or subprogram.
The attribute specification for literal must be declared in the same visibility block as the literal declaration. In case when there are several literals with the same names, the attribute specification for a given literal uses a signature in order to distinguish which type a given literal belongs to (Example 8). If no signature is used the attribute can be applied to all literals with the same name.
When specifying attributes reserved words: others and all can be used as entity (item) names. In the first case, the attribute specification refers to all the remaining visible named entities of a given entity class which do not have the attribute value assigned to them. Such an attribute specification must be the last in the declaration that refers to this attribute. When the keyword all is used, the attribute specification refers to all named entities of the given class. Such an attribute specification must be the first in the declaration part, which relates to this attribute. See Example 9.
Example 1
package Attr_pkg is
attribute Component_symbol : String;
attribute Pin_code : Positive;
attribute Max_delay: Time;
type Point is record
x, y: Real;
end record;
attribute Coordinate : Point;
........
end package Attr_pkg;
The Atrr_pkg contains several attribute declarations, which can be
later specified and used in other design units.
Example 2
package Some_declarations is
use Work.Attr_pkg.Component_symbol,
Work.Attr_pkg.Coordinate,
Work.Attr_pkg.Pin_code,
Work.Attr_pkg.Max_delay;
constant Const_1: Positive
:= 10;
signal Sig_1: Bit_vector (0 to 31);
component Comp_1 is
port
( ... );
end component;
attribute Component_symbol of
Comp_1: component is "Counter_16";
attribute Coordinate of
Comp_1: component is
(0.0, 17.5);
attribute Pin_code of
Sig_1: signal is 17;
attribute Max_delay of
Const_1: constant is
10 ns;
.........
end package Some_declarations;
The package Some_declarations specifies attributes, which were
declared in the package Attr_pkg.
Example 3
package Test_pkg is
attribute Package_atr : String;
attribute Package_atr of Test_pkg:
package is "Training_package";
.........
end package Test_pkg;
The specification of a package attribute Package_atr for the package
Test_pkg is declared in the declaration part of the package.
Example 4
procedure Sub_values (a, b : in
Integer; result: out Integer);
procedure Sub_values (a, b : in
Bit_vector; result: out Bit_vector);
attribute Description : String;
attribute Description of
Sub_values [Integer,
Integer, Integer]:procedure is "Integer_sub_values";
attribute Description of
Sub_values
[Bit_vector, Bit_vector, Bit_vector] :
procedure is "Bit_vector_sub_values";
The specification of the attribute Description intended for
overloaded procedure Sub_values, which subtracts two values of
integer or Bit_vector types, requires signature specification. These
signatures (simplified parameter lists) enable to distinguish
versions of the procedure.
Example 5
function "-" (a, b
: New_logic) return New_logic;
attribute Characteristic : String;
attribute Characteristic of
"-" [ New_logic, New_logic return New_logic]: function is "New_logic_op";
To identify operator ”-” overloaded for two values of type
New_logic it is necessary to use signature that will unambiguously
identify the overloading function.
Example 6
procedure Insert (fifo : inout
Fifo_type; element: in
Elem_type) is
attribute
Number of fifo: variable is 50;
attribute
Trace of element: constant is "Integer/Decimal";
.........
end procedure Insert;
The procedure Insert has two formal parameters of different classes.
Specifications of attributes Number and Trace for parameters fifo and
element, respectively, are placed in the declaration part of the procedure.
Example 7
architecture Struct of
ALU is
component Adder is
port (...)
end component;
attribute Coordinate of
the_Adder: label is (0.0, 0.12);
begin
the_Adder
: Adder port map
( ... );
.........
end architecture Struct;
Specification of the attribute Coordinate for the label the_Adder for
component instantiation statement is located in the declarative part
of the corresponding architecture body Struct.
Example 8
type Three_level_logic is
(Low, High, Idle);
type Four_level_logic is
(Low, High, Idle, Uninitialized);
attribute Hex_value : string
(1 to 2);
attribute Hex_value of
Low [return Four_level_logic]: literal is "F0";
attribute Hex_value of
High [return Four_level_logic]: literal is "F1";
attribute Hex_value of
Idle [return Four_level_logic]: literal is "F2";
attribute Hex_value of
Uninitialized: literal is "F3";
As the literals Low, High, Idle are overloaded, it is necessary to
use signature indicating their type in the specification of the
attribute Hex_value for these literals. However, this is not
necessary for the literal Uninitialized as it is not overloaded.
Example 9
B1: block
signal S1,
S2, S3: Std_logic;
attribute
Delay_attr: Time;
attribute
Delay_attr of all: signal is
100 ps;
begin
.........
end block;
The Delay_attr relates to all signals in the block B1.
Common attributes can be declared for objects of different classes using one construct - group. See the group topic for details.
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