Concurrent Signal Assignment
Concurrent Statement ----used in ----> Architecture
Syntax
signal_name <= expression

signal_name <= expression after delay;

See LRM section 9.5

Rules and Examples
A concurrent signal assignment assigns a new value to the target signal whenever any of the signals on the right hand side change:
architecture CONC of HA is
begin
	SUM   <= A xor B;
	CARRY <= A and B;
end CONC;
Concurrent assignments have an "equivalent process". This is the equivalent process for the concurrent statements above.
architecture SEQ of HA is
begin
	process (A, B)
	begin
		SUM   <= A xor B;
		CARRY <= A and B;
	end process;
end SEQ;

A signal assignment may have a delay specified:

architecture DELAYS of X is
	constant PERIOD : time := 10 ns;
begin
	SUM   <= A xor B after 5 ns;
	CARRY <= A and B after 3 ns;
	CLK   <= not CLK after PERIOD/2;
end DELAYS;

The default delay model is inertial. This means that "pulses" shorter than the delay time are not propagated. The alternative is transport delay, which propagates all transitions:

architecture TRANS of BUFF is
	constant DELAY : time := 10 ns;
begin
	O_PIN   <= transport I_PIN after DELAY;
end TRANS;

Multiple concurrent assignments to the same signal imply multiple drivers. A signal which is the target of multiple concurrent signal assignments must be of a resolved type, e.g. std_logic, std_logic_vector.

For guarded assignments, see blocks
Synthesis Issues

Concurrent signal assignments are generally synthesisable, providing they use types and operators acceptable to the synthesis tool.

A signal assigned with a concurrent statemant will be inferred as combinational logic.

Guarded assignments are not usually supported, and delays are ignored.

Whats New in '93

In VHDL-93, any signal assignment statement may have an optional label:

label: signal_name <= expression;

A delayed signal assignment with inertial delay may be explicitly preceded by the keyword inertial. It may also have a reject time specified. This is the minimum "pulse width" to be propagated, if different from the inertial delay:

OUTPUT <= reject 2 ns inertial not (INPUT) after 10 ns;

A concurrent signal assignment can be specified to run as a postponed process (see process).