Mobile
VHDL Online Help Prev Page Prev Page
Table of Contents
Access Type
Aggregate
Alias
Allocator
Architecture
Array
Assertion Statement
Attributes (predefined)
Attributes (user-defined)
Bit
Bit_Vector
Block Statement
Boolean
Case Statement
Character Type
Component Declaration
Component Instantiation
Composite Type
Concatenation
Configuration Declaration
Configuration Specification
Constant
Delay
Driver
Entity
Enumeration Type
Event
Exit Statement
Expression
File Declaration
File Type
Floating Point Type
Function
Generate Statement
Generic
Group
Guard
Identifier
If Statement
Integer Type
Library Clause
Literal
Loop Statement
Name
Next Statement
Null Statement
Operator Overloading
Operators
Package
Package Body
Physical Type
Port
Procedure
Process Statement
Range
Record Type
Report Statement
Reserved Word
Resolution Function
Resume
Return Statement
Scalar Type
Sensitivity List
Signal Assignment
Signal Declaration
Slice
Standard Package
Std_Logic
Std_Logic_1164 Package
Std_Logic_Vector
String
Subtype
Suspend
Testbench
Type
Type Conversion
Use Clause
Variable Assignment
Variable Declaration
Vector
VITAL
Wait Statement
Waveform

Identifier

Formal Definition

Names that identify various VHDL named entities.

Syntax:

identifier ::= basic_identifier | extended_identifier

basic_identifier ::= letter { [ underline } letter_or_digit }

letter_or_digit ::= letter | digit

letter ::= upper_case_letter | lower_case_letter

extended_indentifier ::= \graphic_character { graphic_character } \

Description

Identifiers are used both as names for VHDL objects, procedures, functions, processes, design entities, etc., and as reserved words. There are two classes of identifiers: basic identifiers and extended identifiers.

The basic identifiers are used for naming all named entities in VHDL. They can be of any length, provided that the whole identifier is written in one line of code. Reserved words cannot be used as basic identifiers (see reserved words for complete list of reserved words). Underscores are significant characters in an identifier and basic identifiers may contain underscores, but it is not allowed to place an underscore as a first or last character of an identifier. Moreover, two underscores side by side are not allowed as well. Underscores are significant characters in an identifier.

The extended identifiers were included in VHDL '93 in order to make the code more compatible with tools which make use of extended identifiers. The extended identifiers are braced between two backslash characters. They may contain any graphic character (including spaces and non-ASCII characters), as well as reserved words. If a backslash is to be used as one of the graphic characters of an extended literal, it must be doubled. Upper- and lower-case letters are distinguished in extended literals.

Examples

Example 1

-- legal identifiers
Decoder_1       FFT            Sig_N      Not_Ack
\signal\        \C:\\Cads\     \Signal @#\

 
All above identifiers are legal in VHDL '93. Note that a single backslash inside an extended name is denoted by two backslashes.

Example 2

-- illegal identifiers
_Decoder_1     2FFT       Sig_#N       Not-Ack

 
No VHDL tool would accept any of the four identifiers above. The errors are as follows: underscore at the beginning of the first identifier, digit at the beginning of the second, special character (#) inside the third and hyphen (special character as well) in the fourth.

Important Notes

  • A basic identifier must begin with a letter.

  • No spaces are allowed in basic identifiers.

  • Basic identifiers are not case sensitive, i.e. upper- and lower-case letters are considered identical.

  • Basic identifiers consist of Latin letters (a..z), underscores ( _ ) and digits (0..9). It is not allowed to use any special characters here, including non-Latin (language-specific) letters.

 

Powered by IXwebhosting