Mobile
VHDL Online Help Prev Page Prev Page
Table of Contents
Access Type
Aggregate
Alias
Allocator
Architecture
Array
Assertion Statement
Attributes (predefined)
Attributes (user-defined)
Bit
Bit_Vector
Block Statement
Boolean
Case Statement
Character Type
Component Declaration
Component Instantiation
Composite Type
Concatenation
Configuration Declaration
Configuration Specification
Constant
Delay
Driver
Entity
Enumeration Type
Event
Exit Statement
Expression
File Declaration
File Type
Floating Point Type
Function
Generate Statement
Generic
Group
Guard
Identifier
If Statement
Integer Type
Library Clause
Literal
Loop Statement
Name
Next Statement
Null Statement
Operator Overloading
Operators
Package
Package Body
Physical Type
Port
Procedure
Process Statement
Range
Record Type
Report Statement
Reserved Word
Resolution Function
Resume
Return Statement
Scalar Type
Sensitivity List
Signal Assignment
Signal Declaration
Slice
Standard Package
Std_Logic
Std_Logic_1164 Package
Std_Logic_Vector
String
Subtype
Suspend
Testbench
Type
Type Conversion
Use Clause
Variable Assignment
Variable Declaration
Vector
VITAL
Wait Statement
Waveform

Variable Assignment

Formal Definition

A variable assignment statement replaces the current value of a variable with a new value specified by an expression.

Simplified Syntax

variable_name := expression ;

Description

The variable assignment statement modifies the value of the variable. The new value of the variable is obtained by assigning an expression to this variable. In order to distinguish variable assignment from signal assignment, the variable assignment symbol is different (:=).

The expression assigned to a variable must give results of the same type as the variable. The target at the left-hand side of the assignment can be either a name of a variable or an aggregate.

In the first case, the target can be in the form of simple name, selected name, indexed name or slice name (Example 1).

In case of aggregate as the target of the assignment, the type of the aggregate must be determinable from the context, including the fact that the type must be of the composite type. Each element of the aggregate must be in the form of the locally static name, which represents variable (Example 2).

The element association of aggregate, similarly to names, may have forms that are more complex: selected name, indexed name or slice name (Example 3).

Examples

Example 1

variable X, Y : REAL;
variable A, B : BIT_VECTOR (0 to 7);
type BIT_RECORD is record
  bitfield : BIT;
  intfield : Integer;
end record;
variable C, D : BIT_RECORD;
X := 1000.0;
A := B;
A := "11111111";
A (3 to 6) := ('1','1','1','1');
A (0 to 5) := B (2 to 7);
A (7) := '0';
B (0) := A (6);
C.bitfield := '1';
D.intfield := C.intfield;

 
The above examples of variable assignments are grouped in the following way: after the declarations the first group is a group of assignments with simple names as targets, then slice names, indexed names and finally selected names.

Example 2

variable E : BIT;
variable I : INTEGER;
(E, I) := C;

 
The aggregate used above as a target for a variable assignment could be used for the variable C declared in such a way as in the Example 1. E will be assigned the value of C.bitfield and I - C.intfield.

Example 3

type BIT_VECTOR_RECORD is record
  a: BIT_VECTOR(0 to 7);
  b: Integer;
end record;
variable G, H : BIT_VECTOR_RECORD;
(C.bitfield, C.intfield) := D; -- aggregate with selected name
(G.a(0 to 7), K) := H; -- aggregate with sliced name
(G.a(0), K) := D; -- aggregate with indexed name

 
Aggregates can use different forms of names.

Important Notes

  • Variable assignment can be labeled.

  • Variable assignment takes effect immediately.

  • Variable assignment can not be specified with a delay.

 

Powered by IXwebhosting