Verilog Online Help   Table of Contents Bit-select Block Statements Built-in Primitives Case Statement Continuous Assignments Conversion Functions Comments Compiler Directives Concatenations Conditional Operator Delays Disable Statement Display Tasks Edge Sensitive Path Expression Bit Length File I/O Functions Functions Identifiers If Statement Integer Constants Intra-assignment Timing Controls Keywords Loop Statements Memories min:typ:max Delays Module Declaration Module Instantiation Module Path Declaration Module Path Polarity Net Data Types Operators Parameters Part-select PLA Modeling Tasks Probabilistic Distribution Functions Procedural Assignments Procedural Continuous Assignments Procedural Timing Control Range Specification Real Constants Register Data Types Simulation Control Tasks Simulation Time Functions Specify Block State Dependent Path Stochastic Analysis Tasks Strengths Strings Structured Procedures Tasks Timescale System Tasks Timing Check Tasks UDP Declaration UDP Instantiation UDP State Table Value Change Dump (VCD) File Vectors

# Bit-select

## Simplified Syntax

vector_identifier[expression];

## Description

The bit-select can be used to access individual bits of vector net or register data types. The bits can be addressed by using an expression. If the expression value is out of bounds or it returns z or x values, then the value returned by the reference is x. If one or more bits of the address returned by the expression have an x or z value, then the address expression is x.

The bit-select can be applied to any net vectors, regs, integers, and time register data types. The bit-selection of a register declared as real or realtime is illegal.

## Examples

Example 1

reg [3:0] vect;
vect = 4'b0001;

If the value of address expression is 0 then returned value is 1 (vect = 1).

If the value of address expression is 3 then returned value is 0 (vect = 0).

If the value of address expression is 4 then returned value is x (vect = x).

If the value of address expression is x or z then returned value is x (vect[1'bx] = x).

Example 2

reg [0:3] vect;
vect = 4'b0001;

If the value of address expression is 3 then returned value is 1 (vect = 1).

If the value of address expression is 0 then returned value is 0 (vect = 0).

Example 3

reg [7:0] vect;
vect = 4;

Fills vect with the pattern 00000100 (MSB is bit 7, LSB is bit 0).

## Important Notes

• If the address expression is out of bounds or it returns an x or z value, then the returned value is x.

• The bit-select of real or realtime registers is illegal.