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Table of Contents
Block Statements
Built-in Primitives
Case Statement
Continuous Assignments
Conversion Functions
Compiler Directives
Conditional Operator
Disable Statement
Display Tasks
Edge Sensitive Path
Expression Bit Length
File I/O Functions
If Statement
Integer Constants
Intra-assignment Timing Controls
Loop Statements
min:typ:max Delays
Module Declaration
Module Instantiation
Module Path Declaration
Module Path Polarity
Net Data Types
PLA Modeling Tasks
Probabilistic Distribution Functions
Procedural Assignments
Procedural Continuous Assignments
Procedural Timing Control
Range Specification
Real Constants
Register Data Types
Simulation Control Tasks
Simulation Time Functions
Specify Block
State Dependent Path
Stochastic Analysis Tasks
Structured Procedures
Timescale System Tasks
Timing Check Tasks
UDP Declaration
UDP Instantiation
UDP State Table
Value Change Dump (VCD) File

Module Path Declaration

Formal Definition

Module path declaration is used to describe how data can propagate through a module.

Simplified Syntax

Simple module path ;

Edge sensitive path ;

State dependent path ;


Let's take a look at this model:

The problem is to define delays between input and output (Y and A for example). The solution is to declare a path and specify a delay. There are three ways to do this:

  • Declare a simple module path

  • Edge a sensitive path

  • State a dependent path.

The idea is to define the delay from the source to the destination. In this method each path can have a specific delay difference. For example, the path between Y and A can be different than Y and B. Generally, if a delay is specified, we know when the response occurs on the output if the input changes.

Examples of module path declarations are also described in chapters: Edge sensitive path, and State dependent path.



Simple module path example:

(A => Q) = 10;
(B => Q) = (12);
(C, D *> Q) = 18;

The symbols *> and => each represent a different kind of connection between the module path source and the module path destination. The operator *> establishes a full connection between source and destination. The operator => establishes a parallel connection between source and destination. Refer to the Language Reference Manual for a description of full connection and parallel connection paths.

Important Notes

  • Module paths cannot be declared outside of a module.

  • Only the net type of a port can be used as a source. Input and inout directions are allowed.

  • Both registers and net types can be used as path destinations. Input and inout directions are allowed.

  • A destination cannot have more than one driver.


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