Mobile
Verilog Online Help Prev Page Prev Page
Table of Contents
Bit-select
Block Statements
Built-in Primitives
Case Statement
Continuous Assignments
Conversion Functions
Comments
Compiler Directives
Concatenations
Conditional Operator
Delays
Disable Statement
Display Tasks
Edge Sensitive Path
Expression Bit Length
File I/O Functions
Functions
Identifiers
If Statement
Integer Constants
Intra-assignment Timing Controls
Keywords
Loop Statements
Memories
min:typ:max Delays
Module Declaration
Module Instantiation
Module Path Declaration
Module Path Polarity
Net Data Types
Operators
Parameters
Part-select
PLA Modeling Tasks
Probabilistic Distribution Functions
Procedural Assignments
Procedural Continuous Assignments
Procedural Timing Control
Range Specification
Real Constants
Register Data Types
Simulation Control Tasks
Simulation Time Functions
Specify Block
State Dependent Path
Stochastic Analysis Tasks
Strengths
Strings
Structured Procedures
Tasks
Timescale System Tasks
Timing Check Tasks
UDP Declaration
UDP Instantiation
UDP State Table
Value Change Dump (VCD) File
Vectors

Comments

Formal Definition

Comments provide a means of describing or documenting a model.

Simplified Syntax

// a single line with comments

/* multiple lines

containing comments */

Description

Comments can be used for describing models. There are two ways of using comments: in a single line or in multiple lines. It is illegal to use '/*' characters without matching '*/' characters. The multiple line comments cannot be nested.

Examples

Example 1

// this is the first line of a single line comment
// this is the second line of a single line comment

Example of a single line comment.

Example 2

/* this is the first line of a multiple line comment
this is the second line of a multiple line comment
*/

Example of a multiple line comment.

Important Notes

  • Using the '/*' characters without the matching '*/' characters is not allowed

  • The multiple line comments cannot be nested

 

Powered by IXwebhosting