Timing Check Tasks
Formal Definition
Timing Check Tasks are for verification of timing properties of
designs and for reporting timing violations.
Simplified Syntax
$setup (data_event,
reference_event, limit[, notifier]) ;
$skew (reference_event,
data_event, limit[,notifier]) ;
$hold (reference_event,
data_event, limit[,notifier]) ;
$recovery (reference_event,
data_event, limit, [notifier]) ;
$setuphold (reference_event,
data_event, setup_limit, hold_limit, [notifier])
;
$width (reference_event,
limit, threshold [,notifier]) ;
$period (reference_event, limit[,notifier])
;
$nochange (reference_event,
data_event, start_edge_offset, end_edge_offset [,notifier])
;
Description
Timing check tasks are invoked every time critical events occur
within given time limits. See the table below with descriptions of
all arguments:
|
Argument |
Description |
Type |
|
Reference_event |
The transition at a control signal that establishes the reference
time for tracking timing violations on the data_event |
Module input or inout that is scalar or vector net |
|
Data_event |
The signal change that initiates the timing check and is monitored
for violations. |
Module input or inout that is scalar or vector net |
|
Limit |
A time limit used to detect timing violations on the data_event |
Constant expression or specparam |
|
Threshold |
The largest pulse width that is ignored by the timing check $width |
Constant expression or specparam |
|
Setup_limit |
A time limit used to detect timing violations on the data_event for $setup. |
Constant expression or specparam |
|
Hold_limit |
A time limit used to detect timing violations on the data_event for $hold. |
Constant expression or specparam |
|
Notifier |
An optional argument that "notifies" the simulator when a
timing violation occurs |
Register |
$setup checks setup time.
When modeling synchronous circuits, flip-flops need time to force a
correct value. Data cannot change within the setup time because
flip-flops cannot detect the new value. If data changes within a
given time limit, $setup
reports a timing violation. If a data event and reference event occur
at the same time there is no violation. The $setup
first checks timing data then records a new data value. The formula
to report a timing violation is as shown below:
(time of reference event) - (time of data event) < limit
Notice that the limit argument has to be a positive number.
$skew checks the following:
(time of data event) - (time of reference event) > limit
$skew can be used to check
synchronicity of clocks inside a circuit. If different clocks are
used in a design and are synchronized, $skew
will report a timing violation when the active edge of one of them
occurs outside the time limit allowed for the other clock to occur.
When the data event and the reference event occur at the same time, $skew
will not report a timing violation.
$hold will report a timing
violation if the following formula is true:
(time of data event) - (time of reference event) < limit
$hold simply checks that
data is stable in the specified interval of time after the edge of
the clock. In flip-flops, data should remain stable for a given time
after the active edge of the clock to allow for propagation of data.
Also, a violation will be reported if the data event and the
reference event occur at the same time.
$recovery responds when the
following formula is true:
(time of data event) - (time of reference event) < limit
The 'reference_event' must be an edge-triggered event: posedge or
negedge. A timing violation occurs if the time interval between an
edge-triggered reference event and a data event exceeds the 'limit'.
If a reference event and data event occur at the same time, a timing
violation is reported. If a 'reference_event' argument is specified
without edge specification, an error is reported.
$setuphold checks setup and
hold timing violations. This task combines the functionality of $setup
and $hold in one task. The
following formula has to be applied:
setup_limit + hold_limit > 0
'reference_event' have to be one of the following:
-
$hold lower bound event
-
$setup upper bound event
'data_event' have to be one of the following:
-
$hold upper bound event
-
$setup lower bound event
In $width both limit and
threshold have to be positive numbers. The 'reference_event' must be
the edge specification, otherwise an error will be reported. The
'data_event' is not specified directly, but by default means
'reference_event' with opposite edge. A timing violation occurs with
the following formula:
threshold < (time of data event) - (time of reference event) < limit
$width reports when width of
the active-edge is too small. In FF case it is very important to
ensure that the width of an active-edge is sufficient and FF will
work properly.
The $period checks that a
period of signal is sufficiently long. The reference_event has to be
an edge specification. The data_event is not specified directly and
by default, is the same as a reference_event. The $period
reports a timing violation when the following formula comes true:
(time of data event) - (time of reference event) < limit
The $nochange checks if the
data signal is stable in an interval of start_edge_offset and
end_edge_offset. If the signal has changed, a timing violation is
reported. The reference_event argument can be posedge or negedge but
the edge control specifiers are disallowed.
Examples
Example 1
module setup (data1, data2, q);
input data1, data2;
output q;
and (q, data1, data2);
specify
specparam tsetup = 7, delay
= 10 ;
(data1 => q) = 10 ;
$setup(data1, posedge
data2, tsetup);
endspecify
endmodule
Example 2
module two_clocks (clk1,
clk2, q);
input clk1, clk2;
output q;
specify
specparam tskew = 7;
$skew(posedge
clk1, posedge clk2, tskew);
endspecify
endmodule
Example 3
module hold (data1, data2, q);
input data1, data2;
output q;
and (q, data1, data2);
specify
specparam thold = 7, delay =
10 ;
(data1 => q) = 10 ;
$hold(posedge data2, data1, thold);
endspecify
endmodule
Example 4
module recovery (in1, out1);
input in1 ;
output out1 ;
assign out1 = in1 ? 1'b1 :
1'bz ;
specify
specparam trecovery = 10;
$recovery(posedge
in1, out1, trecovery);
endspecify
endmodule
Example 5
module setuphold (data1,
data2, q);
input data1, data2;
output q;
and (q, data1, data2);
specify
specparam tsetup = 7,
thold = 7,
delay = 10 ;
(data1 => q) = 10 ;
$setuphold(posedge data2,
data1, tsetup, thold);
endspecify
endmodule
Example 6
module width (data1, data2, q);
input data1, data2;
output q;
and (q, data1, data2);
specify
specparam twidth = 10,
delay = 10 ;
(data2 => q) = 10 ;
$width(posedge data2, twidth);
endspecify
endmodule
Example 7
module dff (clk, q);
input clk;
output q;
buf (q, clk);
specify
specparam tperiod =
100 ;
$period(posedge
clk, tperiod);
endspecify
endmodule
Example 8
module nochange (data1,
data2, q);
input data1, data2;
output q;
and (q, data1, data2);
specify
specparam tstart = -5,
tend = 5 ;
$nochange(posedge data2,
data1, tstart, tend);
endspecify
endmodule
Important Notes
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