Compiler Directives
Formal Definition
Compiler directives are instructions affecting the compilation.
Simplified Syntax
`celldefine
module_declaration
`endcelldefine
`default_nettype net_type_identifier
`define macro_name macro_text
`define
macro_name(list_of_arguments) macro_text
`undef macro_name
`ifdef macro_name
group_of_lines
`else
group_of_lines
`endif
`include "filename"
`resetall
`timescale time_unit / time_precision
`unconnected_drive
module_declaration
`nounconnected_drive
Description
All compiler directives are preceded by an accent grave (`)
character. Compiler directives work from the point where they were
used until the end of compilation or until a point where they are
used again (even if the next usage occurs in another file).
`celldefine and `endcelldefine
These directives mark modules as cell modules (Example 1). They
should be used in pairs outside the module definition.
`default_nettype
This directive sets net type used in implicit net declarations
(Example 2). The default type is a wire. The `default_nettype
directive should be used outside the module definition. The
directive parameter can be one of following types:
wire, tri,
tri0, tri1,
wand, triand,
wor, trior,
trireg.
`define and `undef
These directives define and undefine text macros that can be used as
a text substitution (Example 3). This is very useful in modeling
because all changes can be applied in one place of the source code
(in macro definition).
A macro can be defined with arguments, so every macro call can be
followed by actual parameters.
The compiler recognizes a macro by its name preceded by accent grave
(`) character.
`ifdef, `else, and `endif
These directives can be used to decide which lines of Verilog code
should be included for the compilation (Example 4).
The `ifdef directive checks
if a macro name that follows this directive is defined. If it is,
then all lines between `ifdef
and `else will be included.
Otherwise, only lines between `else
and `endif will be compiled.
`include
The `include directive
(Example 4) inserts the contents of a specified file into a file in
which it was called. The file name should be given in quotation marks
(") and it can be given using full or relative path.
`resetall
This compiler directive turns off all previously used compiler directives.
`timescale
This directive specifies time unit and time precision for simulation
of modules that follow it (Example 5).
The time unit specifies the unit of measurement for times and delays.
The time precision specifies how delay values should be rounded
during the simulation.
The time precision value should be equal or smaller than the time
unit value.
Both time precision and time unit should be made up of an integer
number and a character string that represent a unit of time. The
valid numbers are: 1, 10, and 100. The valid characters are:
s, ms, us, ns, ps, and fs.
Actual time units and time precision values can be displayed by the $printtimescale
system task.
`unconnected_drive and `nounconnected_drive
These compiler directives define how unconnected input ports of
modules should be treated. They should be enclosed between pair of `unconnected_drive
and `nounconnected_drive
directives (Example 6).
The `unconnected_drive takes
one parameter - pull0 or pull1.
If pull0 is used then all
unconnected ports will be pulled down. If pull1
is used then all unconnected ports will be pulled up.
These directives should be used outside any module definition.
Examples
Example 1
`celldefine
module my_and(y, a, b);
output y;
input a, b;
assign y = a & b;
endmodule
`endcelldefine
Module my_and is marked as a cell module.
Example 2
`default_nettype tri
The default net type is set to tri.
Example 3
`define SIZE 8
`define xor_b(x,y) (x &
!y)|(!x & y)
//These text macros can be used as follow:
reg [`SIZE - 1 : 0] data_out;
c = `xor_b(a, b);
`undef SIZE
Example 4
`ifdef behavioral
`include
"groupA_beh.v ";
`include
"groupB_beh.v ";
`include
"ctrl_beh.v ";
`else
`include
"groupA_synth.v ";
`include "groupB_
synth.v ";
`include "ctrl_
synth.v ";
`endif
If a 'behavioral' text macro is defined in a file then the behavioral
models from the files: groupA_beh.v,
groupB_beh.v, and ctrl_beh.v,
will be included. Otherwise synthesizable models from groupA_synth.v,
groupB_synth.v, and ctrl_synth.v,
will be included.
Example 5
`timescale 10 ns / 100 ps
The time unit is set to 10 ns. During the simulation all delay values
will be multiplied by 10 ns, and all delays will be rounded with 100
ps precision.
Example 6
`unconnected_drive pull1
module my_and(y, a, b);
output y;
input a, b;
assign y = a & b;
endmodule
module test;
reg b;
wire y;
my_and u1 (y, ,b);
endmodule
`nounconnected_drive
The a terminal of u1 will be pulled up (set to 1).
Important Notes
|
