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Table of Contents
Block Statements
Built-in Primitives
Case Statement
Continuous Assignments
Conversion Functions
Compiler Directives
Conditional Operator
Disable Statement
Display Tasks
Edge Sensitive Path
Expression Bit Length
File I/O Functions
If Statement
Integer Constants
Intra-assignment Timing Controls
Loop Statements
min:typ:max Delays
Module Declaration
Module Instantiation
Module Path Declaration
Module Path Polarity
Net Data Types
PLA Modeling Tasks
Probabilistic Distribution Functions
Procedural Assignments
Procedural Continuous Assignments
Procedural Timing Control
Range Specification
Real Constants
Register Data Types
Simulation Control Tasks
Simulation Time Functions
Specify Block
State Dependent Path
Stochastic Analysis Tasks
Structured Procedures
Timescale System Tasks
Timing Check Tasks
UDP Declaration
UDP Instantiation
UDP State Table
Value Change Dump (VCD) File

Procedural Timing Control

Formal Definition

The procedural timing control is used to determine when statements should be executed.

Simplified Syntax

Delay control:


  #(min:typ:max delay)

Event type declaration:

  event identifier;

Event trigger:

  -> event_identifier;

Event control:


  @(posedge identifier)

  @(negedge identifier)

  @(event_expression or event_expression)

Wait statement:

  wait (expression) statement


The Verilog HDL has two types of timing controls: delay control (Example 1) and event control (Example 2).

The delay control specifies the time between encountering and executing the statement. The delay control can be specified as a simple delay and as min:typ:max delay.

The named event (Example 3) is a special data type that does not hold any value. The event can be triggered using special characters -> followed by an event identifier. Any occurrence of an event trigger can be noticed using an event control statement.

An event control specifies the event that is required to resume execution of a statement. Event can be one of the following:

  • Named event

  • Change of a signal value

  • Positive or negative edge occurred on signal (posedge, negedge)

  • List of above-mentioned events (separated by or - event or operator)

A posedge is any transition from 0, x, and z to 1, and from 0 to z or x.

A negedge is any transition from 1, x, and z to 0, and from 1 to z or x.

The wait statement (Example 4) will suspend execution of all statements until the expression becomes true.


Example 1


The next statement will be executed after 10 time units.

#10 a = 5;

Assignment to a variable will be delayed by 10 time units.


Delay control with min:typ:max delay value.

#(5:3:7) a = 5;

Assignment to a variable delayed by min:typ:max delay value.

Example 2

@ready a = a + 1;

The 'a' variable will be incremented by 1 when a change occurs on the 'ready' variable.

@(posedge clk) q = d;

The 'd' variable will be assigned to 'q' on the positive edge of clk.

@(a or b or c or d)
y = (a | b) & (~c ^ d);

A new value will be assigned to the 'y' variable when a change occurs on any of the variables a, b, c, or d.

Example 3

event e;

Event declaration.

initial begin
  -> e;

Example of event triggering.

always @e d = 0;

Example of waiting for an event.

Example 4

wait (a);
i = i + 1;
wait (!a);

This sequence of statements will wait until 'a' becomes 1, and then the next statement will be executed. Next, execution will be suspended until 'a' becomes 0.

Important Notes

  • The delay controls are useful in specifying patterns for testbenches.


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